An example of prior art semiconductor memory device of this type is shown in FIG. 1. Its configuration will now be described with reference to the drawings.
FIG. 1 shows the structure of the prior art semiconductor memory device, e.g., dynamic RAM.
This semiconductor memory device has a power supply pad 1 for the ground potential (Vss), and a power supply pad 2 for the power supply potential (Vcc). Connected to the Vss and Vcc power supply pads 1 and 2 are power supply lines 3 and 4, respectively. Connected between the power supply lines 3 and 4 are a plurality of memory cell arrays 10-1 to 10-N. The number of the memory cell arrays 10-1 to 10-N is 8, for example, in the case of a 4 Mbit dynamic RAM. Both supply lines 3 and 4 include line resistance r.
Each of the memory cell arrays 10-1 to 10-N comprises a memory cell matrix 10a of 512 Kbits, for example, a sense amplifier group 10b, and a control circuit 10c for controlling the sense amplifiers 10b. Although not illustrated, peripheral circuits, such as an input circuit for inputting a signal from the outside of the chip, an output circuit for outputting information of the memory cell to the outside, and a writing circuit for writing data from the outside into the memory cells are also connected to the Vss pad 1 and the Vcc pad 2.
In this semiconductor memory device, when a power supply voltage is supplied from the Vss pad 1 and the Vcc pad 2, the power supply voltage is applied via the power supply lines 3 and 4 to the memory cell arrays 10-1 to 10-N. Then the memory cell arrays 10-1 to 10-N operate, and accessing, i.e., data reading or data writing, is performed.
In this type of the semiconductor memory device, as the memory capacity is increased, e.g., up to several Mbits, the length of the conductor of the power supply lines (wiring conductors) 3 and 4 may be as long as several tens of millimeters, and the line resistance of the power supply lines 3 and 4 can be no longer neglected. The power supply lines 3 and 4 disposed from the Vss pad 1 and the Vcc pad 2 and along the memory cell arrays 10-1 to 10-N are therefore formed of a material having a low sheet resistance (such as aluminum) and their width is enlarged in order to to reduce the resistance from the Vss pad 1 and the Vcc pad 2.
A specific example of a semiconductor memory device is shown in FIG. 2, and an example of the memory cell array in FIG. 2 is shown in FIG. 3. Identically labelled elements appearing in the different Figures refer to one in the same element.
As illustrated in FIG. 2, a plurality of memory cell arrays 10-1 to 10-N are connected between the power supply line 3 connected to the Vss pad 1 and the power supply line 4 connected to the Vcc pad 2. The sense amplifiers in each memory cell array 10-1 to 10-N are connected to the power supply line 3 via common nodes N1 supplying a sense latch signal SLN and sense amplifier drive n-channel MOS transistors (NMOS transistors) 11-1 to 11-N that are turned on and off by a control signal SN. The sense amplifiers in each memory cell array 10-1 to 10-N are connected to the power supply line 4 via common nodes N2 supplying a sense latch signal SLP and sense, amplifier drive p-channel MOS transistors (PMOS transistors) 12-1 to 12-N which are turned on and off by a control signal SP.
Also connected to the Vss pad 1 and the Vcc pad 2 are a plurality of peripheral circuits 13-1 to 13-4 for controlling input and output of the semiconductor memory device.
The memory cell arrays 10-1 to 10-N are identical to each other, and one of them, the memory cell array 10-1 is taken up for further explanation with reference to FIG. 3.
The memory cell array 10-1 comprises a memory cell matrix 10a, a sense amplifier group 10b comprising a plurality of sense amplifiers 10b.sub.1 to 10b.sub.P and a control circuit 10c. The control circuit 10c comprises a plurality of word line drive circuits 30.sub.1 to 30.sub.Q, precharge circuits 31.sub.1 to 31.sub.P, transfer gates 32.sub.1 to 32.sub.P, and the like.
The memory cell matrix 10a comprises a plurality of word lines WL.sub.1 to WL.sub.Q, and a plurality of pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P, and memory cells 20.sub.11 to 20.sub.PQ connected at the intersections of the word lines and the bit lines. Each memory cell 20.sub.11 -20.sub.PQ includes a transistor 20a and a capacitor 20b. Connected to the bit line pairs BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P are sense amplifiers 10b.sub.1 to 10b.sub.P. The sense amplifiers 10b.sub.1 to 10b.sub.P are activated by the sense latch signals SLN and SLP on the common nodes N1 and N2, respectively, to detect and amplify the potential difference between each pair of bit lines, and is formed of two NMOS transistors 21a and 21b, and two PMOS transistors 21c and 21d.
The word line drive circuits 30.sub.1 to 30.sub.Q are connected to the word lines WL.sub.1 to WL.sub.Q. The word line drive circuits 30.sub.1 to 30.sub.Q respectively are responsive to the row decode selection signals XD.sub.1 to XD.sub.Q to vary the word lines WL.sub.1 to WL.sub.Q to the high level (Vcc) or to the low level (Vss). The precharge circuits 31.sub.1 to 31.sub.P are connected to the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P for precharging the corresponding pairs of the bit lines to a reference voltage VR responsive to a precharge signal EQ. The transfer gates 32.sub.1 to 32.sub.P are connected to the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P and are turned on and off by a column decode selection signal YD.sub.1 to YD.sub.P to transfer data on the corresponding pairs of bit lines to complementary data lines DB and DB.
FIG. 4 is a waveform diagram for explaining the operation of the circuit of FIG. 3. The operation of FIG. 2 and FIG. 3 will now be described with reference to FIG. 4.
Let us consider the operation of reading data "1" that is stored in the memory cell 20.sub.11 in FIG. 3.
In FIG. 4, the precharge signal EQ of the precharge circuits 31.sub.1 and 31.sub.P precharging the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.P, BL.sub.P to the reference voltage VR (=1/2.Vcc) is lowered from the high level ("H") to the low level to put an end to the precharge. Then, the word line WL.sub.1 is raised to the high level by the word line drive circuit 30.sub.1 to which the column decode select signal XD.sub.1 is input. Then the data "1" in the memory cell 20.sub.11 is output to the bit line BL.sub.1, creating a slight potential difference between the pair of bit lines BL.sub.1, BL.sub.1.
After the word line WL.sub.1 is raised, the control signal SN is raised to the high level and the control signal SP is lowered to the low level. The sense amplifier drive NMOS transistor 11-1 and PMOS transistor 12-1 are turned on, and the sense latch signals SLN and SLP on the common nodes N1 and N2 precharged to the reference voltage VR, through a path not illustrated, are varied to the Vss level and the Vcc level, respectively, so that the sense amplifiers 10b.sub.1 to 10b.sub.P operate. When the sense amplifiers 10b.sub.1 to 10b.sub.P operate, a discharging current I.sub.1 (see FIG. 3) flows from the bit line BL.sub.1 as well as other bit lines BL.sub.2 to BL.sub.P, via the NMOS transistors 21a of the respective sense amplifiers 10b.sub.1 to 10b.sub.P, the common node N1, and the NMOS transistor 11-1 to the power supply line 3, and a charging current I.sub.2 (see FIG. 3) flows via the common node N2, and the PMOS transistor 21d to the bit lines BL.sub.1 to BL.sub.P through the PMOS transistor 12-1 from power supply line 4. By the sensing action of the sense amplifiers 10b.sub.1 to 10b.sub.P, slight potential differences on the pairs of bit lines BL.sub.1, BL.sub.1 to BL.sub.p, BL.sub.P are detected and amplified.
After adequate amplification by the sense amplifiers 10b.sub.1 to 10b.sub.P, the column decode select signal YD.sub.1 is raised from the low level to the high level and the transfer gate 32.sub.1 is turned on, and the potential on the pair of the bit lines BL.sub.1 and BL.sub.1 is transferred to the data bus lines DB and DB. Data is thus read from the desired memory cell 20.sub.11.
In this type of semiconductor memory device, the sense latch signals SLN and SLP are made to operate in a higher speed in order to perform the sensing operation at a higher speed. This can be achieved by increasing the size of the NMOS transistors 11-1 to 11-N and the PMOS transistors 12-1 to 12-N, or the power supply lines 3 and 4 shown in FIG. 2, and the conductors for the common nodes N1 and N2 shown in FIG. 2 are made of metal (e.g., aluminum) having a lower sheet resistance to decrease the resistance.
The above memory device however is associated with the following problems.
(a) In a semiconductor memory device of a large capacity on the order of megabits, the power supply lines 3 and 4 may be as long as 15 mm and the line resistance cannot be neglected. For instance, when the power supply lines 3 and 4 are made of aluminum having a low sheet resistance, the sheet resistance is 0.06 .OMEGA. when the film thickness is 600 angstroms. If the conductor-length/conductor-width from the Vss pad 1 or the Vcc pad 2 to the farthest memory cell array 10-N or 10-1 is 15 mm/100 .mu.m, the line resistance will be 0.06 .OMEGA..times.15000/100=9 .OMEGA.. PA0 (b) With the prior art semiconductor memory devices, it is possible to increase the speed of the sensing operation by enlarging the size of the sense amplifier drive NMOS transistors 11-1 to 11-N and PMOS transistors 12-1 to 12-N, or by using metal of a smaller sheet resistance for the power supply lines 3 and 4 and the conductors for the common nodes N1 and N2. However, increase of the sensing operation may be accompanied with the increase in the charging current I.sub.2 and discharging current I.sub.1, and substantial drop in the Vcc level on the power supply lines 4 and 3 or substantial rise in the Vss level. (See FIG. 4.) When this drop or rise occurs, it acts as a noise giving an adverse effect on the operation after the sense latch, causing access delay or varying the circuit threshold value. Specifically, reduction in the TTL margin of the initial-stage circuit provided in the peripheral circuits 13-1 to 13-4 and operating responsive to TTL level (transistor-transistor logic level) or the like may occur. PA0 (c) A further problem is associated with the differences between in the line resistances for the respective memory cell arrays.
With such a line resistance r, differences are created in the power supply resistance from the Vss pad 1 or the Vcc pad 2 to the respective memory cell arrays 10-1 to 10-N, and differences are created in the operation margin between the memory cell arrays 10-1 to 10-N, and access delays and the like are also created.
As illustrated in FIG. 2, line resistance r is present on the power supply lines 3 and 4, so the power supply resistances at the junctions with the memory cell arrays 10-1 to 10-N differ from each other. For instance, with respect to the memory cell array 10-1, the resistance of the power supply line 3 at the junction with the NMOS transistor 11-1 is small, and the resistance of the power supply line 4 at the junction with the PMOS transistor 12-1 is large. A large Vss noise is created in the vicinity of the Vss pad 1, and the Vcc noise in the vicinity of the Vcc pad 4 is small. In contrast, when the memory cell array 10-N is made to operate the Vss noise in the vicinity of the Vss pad 1 is small, and the Vcc noise in the vicinity of the Vcc pad 2 is large. As a result, the noises in the vicinities of the power supply pads 1 and 2 differ depending on which of the memory cell arrays 10-1 to 10-N is made to operate.
The noises are transmitted via the power supply pads 1 and 2 to the power supply lines 112 and 122 adversely affecting the peripheral circuits connected thereto. In particular, in the input initial-stage circuits receiving RAS (row address strobe), CAS (column address strobe), and other control signals of the TTL level, and operating on the TTL level (not shown), when the memory cell array 10-1 is made to operate, the Vss noise is large, so the high-level-side margin in the input initial-stage circuits declines. When the memory cell array 10-N is made to operate, the Vcc noise is large, so the low-level-side margins declines. Thus, depending on which of the memory cell arrays 10-1 to 10-N operates, the operation margin of the input initial-stage circuits occur may differ and decline, and, as a result, malfunctions of the peripheral circuits including the input initial-stage circuits can occur.